1. Field of the Invention
The present invention relates to a Direct Memory Access (DMA) logic of a half-duplex mode, and more particularly, to a method for avoiding data collisions in a half-duplex mode using direct memory access logic.
2. Background of the Related Art
Transmission systems for data communications typically include simplex and duplex communication methods. The duplex communication method includes a half-duplex transmission and a full-duplex transmission.
The half-duplex transmission is a method in which the direction of data transmission is switched over between two devices to offer each device the opportunity to transmit data to the other. In such a case, concurrent transmitting and receiving is not possible between the two devices.
A Direct Memory Access (DMA) logic is a hardware device that allows transmission and reception of data to be directly controlled. The DMA logic uses a DMA controller (DMAC) to process data between a memory and an input/output unit, without the intervention of a CPU. This has the advantage that it is able to quickly process an input and an output, allowing a large amount of data to be transmitted at a high speed.
FIG. 1 is a schematic block diagram of a related art system of multi-point linked processors for performing a half-duplex transmission.
As shown in FIG. 1, a plurality of processors 11, 12, and 13 are coupled to each other and a RTS/CTS controller 14 with one data bus and two signal lines 21 and 22 in the multi-point linked processors. The plurality of processors 11, 12, and 13 include a transmission control logic (Tx DMA) and a receiving control logic (Rx DMA), respectively, to perform transmitting and receiving of data.
Since the data transmission and reception is carried out over one data bus in the multi-point linked processors, when several processors transmit data at the same time, the data inevitably collides.
Thus, in order to avoid such a data collision, each processor 11xcx9c13 signals its intention to transmit data through the signal line 22 when it desires to transmit a data. Each processor 11xcx9c13 is then controlled by the RTS/CTS controller 14 through the signal line 21. Thus, when the processors 11, 12, and 13 are not transmitting data, they transmit a low level request-to-send (RTS) signal to the RTS/CTS controller 14, signifying a state that data bus is idle.
Upon receipt of the low level RTS signal, the RTS/CTS controller 14 transmits a high level CTS (Clear To Send) signal to all of the processors 11xcx9c13 through the signal line 21, informing that the bus is currently available for data transmission.
Thus, when the processor 11 intends to transmit a data to the processor 13, the transmitting processor 11 changes its low level RTS signal to a high level RTS signal, and initiates the TX DMA logic to start data transmission. When the data transmission of the Tx DMA logic of the transmitting processor 11 is completed, the receiving processor 13 initiates the Rx DMA logic to receive the data.
Additionally, when the data transmission of the Tx DMA logic is completed, the transmitting processor 11 changes its high level RTS signal back to a low level RTS signal, and the RTS/CTS controller 14, receiving the low level RTS signal from the transmitting processor 11, transmits a high level CTS signal to all of the processors 11xcx9c13, indicating that the data bus is in an idle state.
FIG. 2 is a timing diagram depicting the related art data transmission between the multi-point linked processors of a half-duplex transmission mode.
With reference to FIG. 2, a case where the processor 11 has data to be transmitted to processor 13, and processor 13 also has data to be transmitted to processor 11 will be taken as an example for descriptions hereinafter.
When the data bus is in an idle state, processor 11 transmits a high level RTS signal through signal line 22 upon determining the idle state of the data bus. Processor 11 then initiates the Tx DMA logic to transmit data. When the data transmission is completed, processor 11 terminates the Tx DMA logic and changes the high level RTS signal to a low level RTS signal. When the Tx DMA logic has completed, the Rx DMA logic of processor 13 is initiated to receive the data.
In this respect, however, during the transition of the RTS signal, the processor 11 changes the RTS signal from the low level to the high level without confirming whether the Rx DMA logic of the processor 13 has completely received the data.
Meanwhile, the processor 13, which has been monitoring the state of the signal line 21, immediately changes its RTS signal from the low level to the high level when it identifies the idle state of the data bus. Processor 13 then initiates the Tx DMA logic to start data transmission. During this process, processor 13 starts the Tx DMA logic and transmits its data without confirming whether its own Rx DMA logic has completely received the incoming data.
The related art DMA logic has various problems. For example, during the process of transmitting and receiving data, if there is no Tx data on the data bus regardless of the state of the transmitting and receiving processors, that is, the CTS is in a high state, the data is transmitted. Thus, in the related art DMA logic, there is a high possibility of data collision between the Tx DMA logic and the Rx DMA logic of the receiving processor. In addition, concurrent operations of the Tx DAM logic and the Rx DMA logic within the receiving processor can cause a problem of data loss.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
It is an object of the present invention to provide a DMA logic and a method of using the DMA logic which substantially obviates the problems caused by, limitations and disadvantages of the related art.
Another object of the present invention is to provide a method for avoiding data collisions in a half-duplex mode using a DMA logic.
Another object of the present invention is to provide a DMA logic and method thereof that is capable of avoiding a collision between a Tx DMA logic and an Rx DMA logic of a receiving processor when a data is transmitted according to a half-duplex mode.
To achieve at least these there is provided a method for avoiding data collision in a half-duplex mode using a DMA logic for multi-point linked processors in which data is transmitted and received in a half-duplex mode, wherein a transmitting processor holds a request-to-send (RTS) signal in an active state for a predetermined time so that a transmitting DMA logic of a receiving processor can be started after the operation of a receiving DMA logic of the receiving processor is terminated.
To further achieve at least the above objects, there is provided a method for avoiding data collision in a half-duplex mode using a DMA logic for multi-point linked processors in which data is transmitted and received in a half-duplex mode, including the steps of: activating a request-to-send (RTS) signal and transmitting a data from a transmitting processor to a receiving processor through a data bus; holding the RTS signal in an active state when the data is completely transmitted; receiving a data from the transmitting processor for a predetermined time by a receiving DMA logic of the receiving processor; and transmitting a data through the same data bus by a transmitting DMA logic of the receiving processor when the data is completely received.
In the above method, the predetermined time is preferably set the same as the starting time of the Tx DMA of the transmitting processor and varied depending on the length of a transmission data.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.